1. Field of the Invention
The present invention relates to computers and is more particularly concerned with a cache memory structure that has a plurality of reading ports for reading data therefrom and a plurality of ports for writing data thereinto.
2. Description of the Prior Art
Cache memories are well-known in the art in computer architecture. Such memories serve as buffers between operational units that have different data flow rates within a data processing system and communicate with one another. A command computer can be considered as an example, the command computer having the commands to be processed made available thereto from a main memory. These commands must be offered to the computer with shorter access time than is possible given a main memory having comparatively-great memory capacity. The cache memory is operated such that data and commands requested by the command computer during a program run are located in the cache memory with high probability and can therefore be made available with a short access time.
In order to be able to fully utillized the possibilities of large-scale integration (LSI) and in order to enhance the performance capability of the processors, the cache memory is increasingly being integrated on a chip next to the computer hardware core in computer implementation. It should, therefore, be noted that the capacity of the cache memory is being increasingly expanded. This leads to the fact that a cache memory can no longer be economically fully used by a single central processing unit (CPU).